Programming can be accomplished dynamically to reconfigure any of the programmable blocks or the interconnect structure. A complement of Continuous Time CT analog circuit blocks and a complement of Switched Capacitor SC analog circuit blocks are configured to communicate with one another as well as with external devices by means of the interconnect structure.
Standard digital circuit blocks are configured to perform various digital operations including logical decisions and arithmetical computations.
Enhanced digital circuit blocks are configured similarly to the standard digital circuit blocks and have additional digital functions available. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments.
On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention.
However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. Some portions of the detailed descriptions which follow may be presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a microcontroller, or other electronic device.
These descriptions and representations are used by those skilled in the electronic arts to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc.
The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical, electronic, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in an electronic system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, bytes, values, elements, symbols, characters, terms, numbers, streams, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
The present invention provides an on-chip integration of programmable digital and analog circuit blocks in a microcontroller that are able to communicate with each other.
This novel architecture allows a single chip solution to numerous complex activities that would otherwise require multiple chips or separate applications. The dashed line encloses the four major components , , and constructed on the single semiconductor chip.
An important aspect of the present invention is the integration of both programmable analog circuits and programmable digital circuits on the same semiconductor chip. In addition, dynamic programming can be used to change the function of certain analog amplifiers, such as causing an amplifier function to change from simple voltage amplification to digital-to-analog conversion. For instance, programming a digital circuit to perform a logical operation, and reprogramming at a later time to perform a digital counting operation.
The Programmable Interconnect is dynamically programmable and cal be used to couple any analog amplifier to any digital circuit.
Analog Clock signals , Interrupt Controller signals and System Clock signals are connected via the Programmable Interconnect for signal routing as well as dynamic programming of Analog SoCblocks and Digital SoCblocs. Analog signals are coupled to the semiconductor chip at port 0, , which consists of four input pins and four output pins Various interconnect combinations can be used to realize numerous complex analog functions, such as signal amplification, signal filtering, signal filter parameters such as the number and location of poles, and so on.
Digital signals are coupled to the semiconductor chip by means of forty 40 individual pins which form ports 0 through 4, Component reference numbers used are as assigned in FIG. An analog signal to be digitized is presented in step at one of the pins of the analog port 0, in FIG.
Under control of the Analog Clock , the analog input signal is coupled in step via a MUX to the input of an SC1 amplifier configured as an integrator with an internal comparator. In step , the output of the SC1 amplifier is represented as a digital input signal which is applied to two MFBs configured as an eight bit digital counter. What is claimed is: 1. A semiconductor chip comprising: analog circuits;.
The semiconductor chip of claim 1 , wherein the digital circuits are configured to receive the digital signal produced by the analog circuits. The semiconductor chip of claim 1 , wherein the input signal comprises a series of pulses received from a device located external to the semiconductor chip. The semiconductor chip of claim 1 , further comprising a memory element, the memory element to store configuration data, wherein after the digital circuits provide a first digital function, the digital circuits are changeable to provide a second digital function, based on the configuration data.
The semiconductor chip of claim 4 , wherein the memory element to store further configuration data, wherein a parameter of the first digital function is adjustable, based on the further configuration data. USP true USB1 en. USB2 en. System providing automatic source code generation for personalization and parameterization of user modules.
Method for synchronizing and resetting clock signals supplied to multiple programmable analog blocks. Apparatus and method for programmable power management in a programmable analog circuit block. User interface for efficiently browsing an electronic document using data-driven tabs. System and method of dynamically reconfiguring a programmable integrated circuit. System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
Integrated circuit including programmable logic and external-device chip-enable override control. Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks. Method and an apparatus to design a processing system using a graphical user interface. Providing hardware independence to automate code generation of processing device firmware.
Model for a hardware device-independent method of defining embedded firmware for programmable systems. Programmable application specific integrated circuit for communication and other applications. Systems and methods for dynamically reconfiguring a programmable system on a chip. Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes. Dynamically reconfigurable analog routing circuits and methods for system on a chip. Apparatus and method for forming a mixed signal circuit with fully customizable analog cells and programmable interconnect.
EPB1 en. Device for reducing standby-mode energy consumption of an electric household appliance. Electronic control device and method for reducing stand-by state energy consumption of an electric household appliance. Method and apparatus for automatically selecting a plurality of modes for programmable interface circuit by coupling field devices to process controllers.
JPB2 en. USA en. Digital-to-analog converter with current source transistors operated accurately at different current densities. Method of and an arrangement in a telecommunication system for regulating the phase position of a controlled signal in relation to a reference signal. Schematic diagram generating system using library of general purpose interactively selectable graphic primitives to create special applications icons.
Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations. Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory. EPA2 en. Method and apparatus for synchronizing clocks prior to the execution of a flush operation. Compensation circuit for nullifying differential offset voltage and regulating common mode voltage of differential signals.
EPA1 en. Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier. No-chip debug peripheral which uses externally provided instructions to control a core processing unit. JPHA en. Non-impact printer with token bit control of data and current regulation signals. Real-time tracing of dynamic local data in high level languages in the presence of process context switches. Filtered detection plus propagated timing window for stabilizing the switch from crystal to ring oscillator at power-down.
Multiple frequency phase-locked loop clock generator with stable transitions between frequencies. Block diagram system and method for controlling electronic instruments with simulated graphic display. Voltage regulator for generating a constant reference voltage which does not change over time or with change in temperature.
System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data. Apparatus for performing multiply and accumulate instructions with reduced power and a method therefor. Integrating photosensor and imaging system having wide dynamic range with varactors. Method and apparatus for performing neighborhood operations on a processing plane. Resume control system and method for executing resume processing while checking operation mode of CPU.
Differential input circuit and operational amplifier with wide common mode input voltage range. High-density photosensor and contactless imaging array having wide dynamic range. Voltage controlled oscillator operating with digital controlled loads in a phase lock loop. Apparatus for interfacing analog telephones and digital data terminals to an ISDN line. Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC. Structures for electrostatic discharge protection of electrical and other components.
Processing system for providing an in circuit emulator with processor internal state. End pulse width modulation for digital image printer with halftone gray scale capability.
Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks and exchangers. Two layer neural network comprised of neurons with improved input range and input offset. Hans List. Method and apparatus for facilitating operator reconfiguration of a graphical user interface in a data processing system. Selecting and locating graphical icon objects to define and configure the workstations in data processing networks. Virtual right leg drive and augmented right leg drive circuits for common mode voltage reduction in ECG and EEG measurements.
Integrated circuit having controller impedances and application to transceivers, in particular for communication between units of a system. Second order Sigma-Delta based analog to digital converter having superior analog components and having a programmable comb filter coupled to the digital signal processor.
System and methods for improved spreadsheet interface with user-familiar objects. Programmable logic device which stores more than one configuration and means for switching configurations. Voltage controlled oscillator VCO with symmetrical output and logic gate for use in same.
Method and apparatus for providing a modified temperature compensation signal in a TCXO circuit. Temperature compensated constant-voltage circuit and temperature compensated constant-current circuit. Programmable logic device including a parallel input device for loading memory cells.
Microcontroller emulator for plural device architecture configured by mode control data and operated under control code transmitted via same switching bus. Programmable logic module and architecture for field programmable gate array device. Dual socket upgradeable computer motherboard with automatic detection and enablement of inserted upgrade CPU chip. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array.
Dual port memory having a plurality of memory cell arrays for a high-speed operation. WOA1 en. Integrated circuit having programmable analog modules with configurable interconnects between them. Method and apparatus for producing a composite second image in the spatial context of a first image. Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits.
Technique for automatically adapting a peripheral integrated circuit for operation with a variety of microprocessor control signal protocols. High precision voltage regulation circuit for programming multilevel flash memory. Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation. WOA2 en. Programmable logic array device with grouped logic regions and three types of conductors. System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices.
Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation. Peak and valley signal measuring circuit using single digital-to-analog converter.
Signal conditioning apparatus and method exhibiting accurate input impedance and gain characteristics over common mode range and operational environments. Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses. Level converter including wave-shaping circuit and emulator microcomputer incorporating the level converter. High speed product term allocation structure supporting logic iteration after committing device pin locations.
Semiconductor integrated circuit for developing a system using a microprocessor. Integrated microcontroller having a cup-only mode of operation which directly outputs internal timing information for an emulator. Use of between-instruction breaks to implement complex in-circuit emulation features.
Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions. Asynchronous processor access to a switch table in a network with isochronous capability. Arbitration protocol for a bidirectional bus for handling access requests to a logically divided memory in a multiprocessor system. System development and debug tools for power management functions in a computer system. Magnetic disk storage apparatus with phase sync circuit having controllable response characteristics.
Systems utilizing a single chip microcontroller having non-volatile memory devices and power devices. Apparatus for reducing jitter of a spectrum spread clock signal and method therefor. Microcomputer free from control of central processing unit CPU for receiving and writing instructions into memory independent of and during execution of CPU. Supervisory control system for networked multimedia workstations that provides reconfiguration of workstations by remotely updating the operating system.
Safe and low cost computer peripherals with force feedback for consumer applications. Intelligent real-time graphic-object to database linking-actuator for enabling intuitive on-screen changes and control of system configuration.
Multiprocessing system employing an adaptive interrupt mapping mechanism and method. User-directed method for operating on an object-based model data structure through a second contextual image. Microcontroller with security logic circuit which prevents reading of internal memory by external program. Method and apparatus for providing precise fault tracing in a superscalar microprocessor. CAD and simulation system for targeting IC designs to multiple fabrication processes.
Automatic communication protocol detection system and method for network systems. Method and apparatus for error compensation using a non-linear digital-to-analog converter. System and method for extending the drag function of a computer pointing device. Latching inputs and enabling outputs on bidirectional pins with a phase locked loop PLL lock detect circuit. Portable electronic apparatus and charge controlling method for portable electronic apparatus. Method and apparatus for extending the signal path of a peripheral component interconnect bus to a remote location.
Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD. Method and apparatus for providing clock signals to macrocells of logic devices. Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed. Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information.
Method, apparatus and application for object selective but global attribute modification. System and method for simulating signal flow through a logic block pattern of a real time process control system. Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices. Process for the prototyping of mixed signal applications and field programmable system on a chip for applying said process.
Dual function disk drive integrated circuit for master mode and slave mode operations. DEC1 en. Serial communication interface system having programmable microcontroller for use in a battery pack. Voltage regulator for semiconductor non-volatile electrically programmable memory device. Semiconductor device comprising polysilicon interconnection layers separated by insulation films.
Processor supervisory circuit and method having increased range of power-on reset signal stability. System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description. Tile-based modular routing resources for high density programmable logic device.
DEC2 en. Field programmable gate array with distributed RAM and increased cell utilization. Three-pin buck and four-pin boost converter having open loop output voltage control. Method of executing perform locked operation instructions for supporting recovery of data consistency if lost due to processor failure, and a method of recovering the data consistency after processor failure.
Semiconductor structure design and process visualization through the use of simple process models and intuitive interfaces. Remote program monitor method and system using a system-under-test microcontroller for self-debug.
Capacitor array having user-adjustable, manufacturer-trimmable capacitance and method. Method and system for designing and analyzing optical application specific integrated circuits. Method and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniques.
Dynamically reconfigurable FPGA apparatus and method for multiprocessing and fault tolerance. Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models. Method and apparatus for controlling the common-mode output voltage of a differential buffer. Self-adjusting startup control for charge pump current source in phase locked loop.
Method of estimating power consumption of each instruction processed by a microprocessor. Power supply having means for extending the operating time of an implantable medical device.
Trimmable circuitry for providing compensation for the temperature coefficients of a voltage controlled crystal-less oscillator. Large scale integrated circuit having functional blocks controlled with clock signals that conduct setting operations at different times. Debugging apparatus for debugging a program by changing hardware environments without changing program operation state.
Graphical programming system and method including three-dimensional nodes with pre-defined input and output capabilities. System for writing a plurality of data bits less than from the total number of bits in a data register using a single register write operation. Circuitry for providing external access to signals that are internal to an integrated circuit chip package.
Phase-locked loop with protected output during instances when the phase-locked loop is unlocked. Digital compensation for wideband modulation of a phase locked loop frequency synthesizer. Field programmable gate array with dedicated computer bus interface and method for configuring both.
Collaboration centric document processing environment using an information centric visual user interface and information presentation method. Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time. Data processing system for controlling execution of a debug function and method thereof. Synchronous sense amplifier with temperature and voltage compensated translator. System and method for configuring and managing resources on a multi-purpose integrated circuit card using a personal computer.
Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory. System and method for simulation of integrated hardware and software components. System and method of memory access in apparatus having plural processors and plural memories.
Signal converter with a dynamically adjustable reference voltage and chipset including the same. Computer interconnection system having analog overlay for remote control of the interconnection switch. Method and device for communicating across a chip boundary including a serial-parallel data packet converter having flow control logic.
Synthesis-friendly FPGA architecture with variable length and variable timing interconnect. Programmable interconnect matrix architecture for complex programmable logic device. Single chip communication device that implements multiple simultaneous communication channels. Method for initializing an electronic device using a dual-state power-on-reset circuit. Digital phase detector and charge pump system reset and balanced current source matching. Method and apparatus for improving the performance of an aperture monitoring system.
Non-intrusive in-system debugging for a microcontroller with in-system programming capabilities using in-system debugging circuitry and program embedded in-system debugging commands. Using multiple high speed serial lines to transmit high data rates while compensating for overall skew. Methods and apparatus for automatically generating interconnect patterns in programmable logic devices.
Linux Users For those who don't have 'wget' installed on your machine, you can simple replace the 'wget' command with: 'curl -O -J'. Great content tho! I did not know i could download multiple files by copying them all at once and pasting on the terminal.
Thanks for the suggestions on adding the why-reactive. Feel free to comment and I can add more :. Thanks a lot for the resources! I am now drawing up a development plan for the next year, so I will add it to my list. For example, I would like to read Hamlet. This is from the school program, hehe. Skip to content. Sign in Sign up. Instantly share code, notes, and snippets.
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